数电

4.组合电路

组合电路

Multiplexer

数学表达式

$$ Z = \Sigma_{i=0}^{n-1} \ m_i D_i $$

74x151 - 压缩卡诺图

2-1 Multiplier

加法器

Full Adder

  1. 过程

  1. 真值表与实现效果

$$ x_i + y_i + c_i = s_i \\\ \\ 溢出到c_{i+1} $$

  1. 逻辑表达

$$ \begin{aligned} s_i &= SOP \\ c_{i+1} &= POC \\ s_i &= x_i \oplus y_i \oplus z_i \\ c_{i+1} &= x_iy_i + c_i(x_i \oplus y_i) \end{aligned} $$

  1. 电路

  1. 逻辑符号

  1. Verilog Code for a 1-bit FA
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module FA(
    input x,y,c0,
    output s,c1
);
    assign s = x^y^c0;
    assign c1 = (x & y) | (c0 & (x^y));
endmodule

Ripple-Carry Adder (串位进行加法器)

  1. 定义
  • 级联多个FA, 每一个FA都要等待上一位的输出，效率低下
  1. 通过 RCA实现4-bit adder

  1. Verilog
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module Adder4(
    input A,B;
    output Sum;
    output Cout
);
    assign {Cout,Sum} = A + B; // 多路赋值
endmodule

Carry-Lookahead Adder (进位预测加法器)

  1. 只适用于无符号数

  2. 前提与分析

$$ \begin{aligned} c_{i+1} &= x_iy_i + (x_i + y_i)c_i \\\ \\ Let \ g_i &= x_iy_i \\ \ p_i &= x_i + y_i \\\ \\ c_1 &= g_0 + p_0c_0 \\ c_2 &= g_1 + p_1c_1 \\ &= g_1 + p_1(g_0 + p_0c_0) \\ &= g_1 + p_1g_0 + p_ip_0c_0 \\ c_3 &= g_2 + p_2g_1 + p_2p_1g_0 + p_2p_1p_0c_0 \\ c_4 &= g_3 + p_3g_2 + p_3p_2g_1 + p_3p_2p_1g_0 + p_3p_2p_1p_0c_0 \end{aligned} $$

  1. 电路

减法器 (无符号数)

输出

实现方式

$$ \begin{aligned} 被减数为B,减数为A \\ A-B &= A+(-B) \\ 通过补码,-B &= B’ + 1 \\ 因此, F &= A - B = A+ B’ +1 \end{aligned} $$

逻辑函数与其他参数

$$ \begin{aligned} d_i &= x_i \oplus y_i \oplus z_i \\ b_{i+1} &= x_i’b_i + x_i’y_i + y_ib_i \end{aligned} $$

加法和减法器的结合

原理 真值表 电路 逻辑符号

溢出的处理与公式

$$ \begin{aligned} 减法: Signed \ Overflow &= (A_n\cdot B_n’ \cdot F_n’) + (A_n’\cdot B_n\cdot F_n) \\ 加法: Signed \ Overflow &= (A_n’ \cdot B_n’ \cdot F_n) + (A_n\cdot B_n\cdot F_n’) \end{aligned} $$

Verilog实现代码

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module AddSub (
	input S, // select 0=add, 1=subtract
	input [3:0] A, B,
	output reg [3:0] F,
	output reg Unsigned_Overflow,
	output reg Signed_Overflow
);

reg [4:0] TempF;

always @ (S or A or B) begin
	if (S == 0) begin // addition
	// zero extend A and B before add
		TempF = {1'b0,A} + {1'b0,B};
		F = TempF[3:0];
		Unsigned_Overflow = TempF[4];
		// Signed overflow = MSB of A'B'F + ABF'
		Signed_Overflow = ((!A[3]) & (!B[3]) & (TempF[3])) +
		((A[3]) & (B[3]) & (!TempF[3]));
	end
	else begin // subtract
		// zero extend A and B before subtract
		TempF = {1'b0,A} - {1'b0,B};
		F = TempF[3:0];
		Unsigned_Overflow = TempF[4];
		// Signed overflow = MSB of AB'F' + A'BF
		Signed_Overflow = ((A[3]) & (!B[3]) & (!TempF[3])) +
		((!A[3]) & (B[3]) & (TempF[3]));
	end
end
endmodule

ALU

4位ALU电路和逻辑符号

操作表 真值表

  • 通过卡诺图化简(只考虑$s_2 = 0 \ or \ 1$, 这样就只有四个变量)

组成单元

LE (Logic Extender)

AE (Arithmatic Extender)

CE (Carry Extender)

Verilog代码

行为代码

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module alu (
	input [2:0] S,
	input [n-1:0] A, B,
	output reg [n-1:0] F
	);
	parameter n = 4;

	always @ (S or A or B) begin
		case (S)
			0: F = A;
			1: F = A & B;
			2: F = A | B;
			3: F = ~A;
		
			// bitwise NOT
			4: F = A + B;
			5: F = A - B;
			6: F = A + 1;
			7: F = A - 1;
		endcase
	end
endmodule

数据流和结构代码

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module LE (
	input [2:0] s,
	input ai, bi,
	output xi
);
// using the equation derived for the LE
	assign xi = (s[2] & ai) | (~s[0] & ai) | (~s[1] & ai & bi) |
	(~s[2] & s[1] & ~ai & (bi | s[0]));
endmodule

module AE (
	input [2:0] s,
	input bi,
	output yi
);
// using the equation derived for the AE
	assign yi = (s[2] & s[0] & (s[1] | ~bi)) | (s[2] & ~s[1]
	& ~s[0] & bi);
endmodule

module CE (
	input [2:0] s,
	output c0
);
// using the equation derived for the CE
	assign c0 = (s[2] & (s[1] ^ s[0]));
endmodule

module FA (
	input ci, xi, yi,
	output ci1, fi
);
// using the equations derived for the FA
// bitwise &=AND; |=OR; ^=XOR
	assign ci1 = (xi & yi) | (ci & (xi ^ yi));
	assign fi = xi ^ yi ^ ci;
endmodule

module bitslice (
	input [2:0] s,
	input ai, bi,
	input ci,
	output ci1, fi
);

	wire xi, yi;
	// each bit slice consists of the LE, AE and FA
	LE U2(s, ai, bi, xi);
	AE U1(s, bi, yi);
	FA U0(ci, xi, yi, ci1, fi);
endmodule

module alu (
	input [2:0] S,
	input [n-1:0] A, B,
	output [n-1:0] F,
	output Unsigned_Overflow, Signed_Overflow
);
	parameter n = 4;
	wire [n:0] C;
	// only correct for this one
	assign Unsigned_Overflow = C[4] ^ S[0];
	assign Signed_Overflow = C[4] ^ C[3];
	// top level: connect the four bit slices and the CE together
	bitslice U3(S, A[3], B[3], C[3], C[4], F[3]);
	bitslice U2(S, A[2], B[2], C[2], C[3], F[2]);
	bitslice U1(S, A[1], B[1], C[1], C[2], F[1]);
	bitslice U0(S, A[0], B[0], C[0], C[1], F[0]);
	CE U4(S, C[0]);
endmodule

Decoder

电路和逻辑符号

Verilog

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module decoder(
	input A,B,C,
	output reg [7:0] Y
);
	always@(*)
	begin
		Y[0] = (~A) & (~B) & (~C);
		Y[1] = (~A) & (~B) & (C);
		Y[2] = (~A) & (B) & (~C);
		Y[3] = (~A) & (B) & (C);
		Y[4] = (A) & (~B) & (~C);
		Y[5] = (A) & (~B) & (C);
		Y[6] = (A) & (B) & (~C);
		Y[7] = (A) & (B) & (C);
	end
endmodule

Encoder

74x148 Encoder

  1. 电路图

  1. 工作原理

Verilog

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module decoder(
	input [7:0] in,
	output reg [2:0] out
);

	always @ (in) 
	begin
    	case (in)
        	8'b00000001: out = 3'b000;
        	8'b00000010: out = 3'b001;
        	8'b00000100: out = 3'b010;
        	8'b00001000: out = 3'b011;
        	8'b00010000: out = 3'b100;
        	8'b00100000: out = 3'b101;
        	8'b01000000: out = 3'b110;
        	8'b10000000: out = 3'b111;
        	default: out = 3'b000;
    	endcase
	end
endmodule

Tri-State Buffer

性质与作用

  1. 三种状态: 高电平、低电平、高阻态(等价于断路)

  2. 放大输入信号后输出

  3. 高阻态下不干扰其他电器工作

电路和逻辑符号

Verilog

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module TriState_Buffer
	#(parameter n = 4)(
	input E,
	input [n-1:0] D,
	output [n-1:0] Y
    );
	assign Y = (E) ? D : {n{1'bz}};
endmodule

Comparator

常见的四位比较器

4-bit X > Y Comparator

  1. 设计

  1. Verilog (Behavioral Code)
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module Greater(
	input [3:0] X,Y;
	output G
);
	assign G = (X > Y) ? 1'b1 : 1'b0;
endmodule

Shifter

类型

4-bit Shifter

Verilog

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module shifter(
	input [1:0]S;
	input [7:0]data_in;
	output reg [7:0]date_out;
)
	always @(S or date_in)
	begin
		case(S)
		0: data_out = date_in;
		1: data_out = date_in << 1;
		2: data_out = date_in >> 1;
		3: data_out = {date_in[0],data_out[7:1]};
		endcase
	end
endmodule

Multiplier

原理 电路图

Verilog

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module Multiplier(
	input [3:0] M,Q,
	output [7:0] P
);
	P = M*Q;
endmodule

Parity Generator/Checker

电路

  1. 校验位
  • 奇数为1. 偶数为0

Verilog

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module parity_checker(
	input DB[7:0];
	output EVEN, ODD
);
	ODD = DB[0]^DB[1]^DB[2]^DB[3]^DB[4]^DB^[5]^DB[6]^DB[7];
	EVEN = ~ODD;
endmodule

门电路

Fan

Fan-in (of a logic family)

The number of inputs that a gate can have in a particular logic family

Fan-out (of a logic family)

The number of outputs that a gate can have in a particular logic family

CMOS反相器

电路

图像

  • 低电位时，PMOS导通，NMOS截止

  • 高电位时，PMOS截止，NMOS导通

CMOS 逻辑系列电平规格

上/下拉电阻

  1. 上拉$p$电阻

$$ 上拉电阻 \ R_{p(on)} = \frac{V_{CC} - V_{OHminT}}{|I_{OHmax}|} $$

  1. 下拉$p$电阻

$$ R_{n(on)} = \frac{V_{OLmax}}{I_{OLmax}} $$

  1. Schmitt-trigger Inverter

  • 当输入信号超过阈值时，输出信号会发生反转

  • 具有高的噪声抑制能力和稳定性

与非门

  • 最多6输入

或非门

  • 最多4输入

非反相门

与或非门

附录

有源电路

  • 有源电路是指包含电源或其他能够提供电能的元件的电路，例如电子管、晶体管、集成电路等

与非门最快,最便宜

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