数电

5.时序电路

Bistable Element

  • 串联两个Inverter达到保持input和output都不变的效果

SR Latch (Set Reset) - SR 锁存器

与非门

或非门

Gated SR Latch / S Latch With Enable (NAND)

D Latch (NAND)

  • 效果:输出端保持稳定

Gated D Latch

  1. 2 NAND

  1. 4 NAND

Verilog Code

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module D_Latch_With_Enable(
	input E,
	input D,
	output reg Q
);
	always @(E or D)
	begin
	if (E)
		Q <= D;
	end
endmodule

总结

NAND NOR
输入为$11$是不稳定的 输入为00是不稳定的

Clock Divider

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module clock_divider
#(parameter [24:0] half = 25'd6250000) // 指定时钟分频的周期
(
	input clock_in, // 50MHz Input Clock
	output reg clock
    );
	reg [24:0] count;

	always @ (posedge clock_in)
	begin
        if (count == half)
        begin
			count <= 1'd0;
			clock = ~clock;
        end
		else
			count <= count + 1;
	end
endmodule

D Flip-Flop

定义

当时钟输入端接收到一个时钟信号时，将数据输入端的状态存储下来，并在下一个时钟信号到来前保持不变

Behavioral Verilog

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module flipflop( // 无Enable的
	input D,
	input clock,
	output reg Q
);
	always @(posedge clock)
		Q <= D;
endmodule

module D_flipflop( // 多了使能和重置
	input Clock,
	input D,
	input Enable,
	input Clear,
	output reg Q
)
	always @(posedge Clear or posedge Clock)
	begin
		if (Clear == 0)
			Q <= 0;
		else if (Enable)
			Q <= D;
	end
endmodule

Master-slave positive edge-triggered D flip-flop

用SR-Latch 实现 D Flip-Flop

描述 - 状态图 方程 特征表

stateDiagram Q=0 --> Q=1: D=1 Q=0 --> Q=0: D=0 Q=1 --> Q=0: D=0 Q=1 --> Q=1: D=1

$$ Q_{next} = D $$

master-slave negative edge-triggered D flip-flop

D flip-flop With Enable

Register File

定义

存储CPU中的通用寄存器

Register Verilog

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module register
#(parameter n = 4)
(
	input Clock,Clear,Load,
	input [n-1:0] D,
	output [n-1:0] Q
    );
	always @(posedge Clock or posedge Clear)
	begin
		if(Clear == 1)
			Q <= {n{1'b0}};
		else if (Load)
			Q <= D;
	end
endmodule

4 location x 8-bit Register File Circuit

WA Write Address
WE Write Enable
RAA Read A Address
RAE Read A Enable
RBA Read B Address
RBE Read B Enable

Register File Verilog

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module register_file( // 四个Register
    input Clock,
    input WE,
    input [1:0] WA,
    input [7:0] D,
    input RAE,RBE,
    input RAA,RBA,
    output reg [7:0] PortA,
    output reg [7:0] PortB // 注意输出是reg变量
);
    reg [7:0] reg0,reg1,reg2,reg3;
    
    always@(posedge Clock)
    begin
        if(WE)
            case(WA)
                0: reg0 <= D;
                1: reg1 <= D;
                2: reg2 <= D;
                3: reg3 <= D;
            endcase
        end
    
    always @(RAA, RAE)
    begin
        if (RAE)
            begin
            case (RAA):
            0: PortA <= reg0;
            0: PortA <= reg2;
            0: PortA <= reg2;
            0: PortA <= reg3;
            dafault: PortA <= 8'h00;
            endcase
            end
        else
            PortA <= 8'h00;
    end

    always @(RAA,RBE)
    begin
        if (RBE)
            begin
            case (RBA):
            0: PortB <= reg0;
            0: PortB <= reg2;
            0: PortB <= reg2;
            0: PortB <= reg3;
            dafault: PortB <= 8'h00;
            endcase
            end
        else
            PortB <= 8'h00;
    end
endmodule

4-bit bidirectional, parallel-in, parallel-out Register

74x194

Function table

内存

ROM

逻辑符号 操作表

Verilog

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module ROM
#(parameter size = 4)
(
	input [size-1:0] Address,
	input EO,
	output [7:0] D
    );
	reg [7:0] mem[0:2**size-1];

	initial	begin
		mem[0] <= 8'b01100000; // IN A
		mem[1] <= 8'b10000000; // OUT A
		mem[2] <= 8'b10100000; // DEC A
		mem[3] <= 8'b11000001; // JNZ 0001
		mem[4] <= 8'b11111111; // HALT
	end

	assign D = (OE) ? mem[Address]: 8'bz;
endmodule

RAM

逻辑符号 操作表

$4\times 4$ RAM

经典RAM Verilog 代码

CE WR EO
Chip Enable Write Enable Output 
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module RAM
#(parameter size =5)
(
	input CE,WR,OE,
	input [7:0] Data,
	output [size-1:0] Address
);
	reg [7:0] mem[0:2**size-1];
	reg [7:0] data_out;

	assign Data = (CE & OE & ~WR) ? data_out: 8'bz; // Data should output the previously stored value which can be accessed from data_out
	always@(*) begin
        if(CE && WR)
		    mem[Address] = Data;
	end

	always@(*)
    begin
        if (CE & OE & ~WR)
            data_out = mem[Address];
    end
endmodule

$32\times 8$ RAM used in EC-2 Microprocessor

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module ram(
    #(parameter size=5)
    input Clock,
    input Reset,
    input WE,
    input [size-1:0] Address,
    input [7:0] D,
    output reg [7:0] Q
);

reg [7:0] mem[2**size-1:0];

always @(posedge Clock or posedge Reset) begin
    if (Reset) begin
    mem[0] <= 8'b10000000; // IN A
    mem[1] <= 8'b01111111; // SUB A,11111
    mem[2] <= 8'b10100100; // JZ 00100
    mem[3] <= 8'b11000001; // JPOS 00001
    mem[4] <= 8'b11111111; // HALT
    mem[31]<= 8'b00000001; // storage for the constant 1
    end 
    else begin
        if (WE)
        mem[Address] <= D;
    end
end // always

always @ (Address) begin
    Q <= mem[Address];
end
endmodule

Shift Register

4-bit serial-to-parallel register

Right Shift Register

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module ShiftReg
(
	input Serial_in,
	input Clock,
	input Shift,
	output reg [3:0] Q
);
	reg [3:0] value = 0;
	
	always @(posedge Clock)
	begin
		if (Shift)
			Q <= {Serial_in,Q[3:1]}; // 将Serial_in和Q[3:1]连起来
	end
endmodule

Counter

4-bit Binary Up Counter

Verilog

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module Counter(
	input Clock,
	input Clear,
	input Up,
	output [3:0] Q
);
	reg [3:0] Value;

	always @(posedge Clear or posedge Clock)
	begin
		if (Clear)
			Value <= 0;
        else if (Up)
			Value <= Value + 1;
		else
			Value <= Value - 1;
	end
	assign Q = Value;
endmodule

74x163 - 4-bit Binary Synchronous Counter

RCO (Reset Carry-Out)

  • 复位同步输出引脚。当计数器达到最大计数值时，RCO引脚会输出一个脉冲信号，用于将其他电路中的计数器复位或同步。用于同步多个计数器的计数。

Shift-Register Counters

定义

将一个二进制数字序列存储在移位寄存器中，然后通过移位操作将其向左或向右移动，从而实现计数。当移位寄存器中的数字序列达到最大值时，计数器会重新开始计数。可以使用单个移位寄存器或多个级联的移位寄存器来实现不同的计数分辨率

Ring Counters

电路

状态

  1. 主状态(有效状态)

  1. 无效状态

Self-Correcting

Johnson Counter (扭环计数器)

电路

状态

  1. 有效状态

  1. 无效状态

Self-Correcting

Linear Feedback Shift Register Counters (LFSR)

Serial Signal Generator

Example - Serial Signal Generator (110100)

Dff (D触发器)

163 -> 151

Shift Register

Timing Analysis

Timing issue

  • 时钟偏移、信号延迟、时序失配、时序噪声等

Hazards in Digital System

定义

Combinational Circuit 中出现的不期望的输出

Static hazard (glitch)

  1. Static 1 hazard
  • the output changes from 1 to 0 and back to 1
  1. Static 0 hazard
  • the output changes from 0 to 1 and back to 0

Dynamic hazard (bounce)

  • Dynamic 0 to 1 hazard: the output changes from 0 to 1 to 0 to 1

  • Dynamic 1 to 0 hazard: the output changes from 1 to 0 to 1 to 0

Synchronous & Asynchronous

  1. Preset = Set, Clear = Reset

  2. 在时钟的上升/下降沿改变的信号叫做同步信号, 否则是异步信号

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