基本格式

语法

地址

Endianess (Bit Order)

• The ARM processor is little endian by default; and can be programmed to operate as big endian

Wtite Assembly for ARM

回顾

ISA (Istruction Set Architecture)

1. 信息的获取和存储

• Memory

• Register

• I/O Devices

2. 信息的处理

• Assembly-Language Instructions

• Hardware Process Actions

RISC

1. Load

2. Store

3. Data Path & Control Unit

4. Instruction Pipelines

重要单元结构

Arm Register File

• PC 存储下一条指令的地址

Cortex-M Memory Map (内存图)

1. 32位支持$2^{32} = 2^{30} \times 2^2 =4G$ 内存

2. Code、Data、I/O 共用内存

3. 数据类型: Bytes, words, halfwords

4. 内存地址类型: Bytes

• Vendor Specifc: 针对某个厂商的

Data Path & Control Unit

Instructions

1. Arithmatic、Logic、Comparison Operation

2. Data Movement between Registers

Registers

1. Saved Register: R4-R11, hold variables

2. Temporary Register: R0-R3, R12, hold intermediate values

指令 助记符 标志位 标签

ARM Cortex-M的汇编指令

ARM ALU*

Conditional Flag (CNVZ)

1. 标识位解释

2. 助记符

3. 示例(Conditional Opcode)

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CMP R1 R2
SUBNE R3, R5, R8 ; 只有当R1 != R2 时才能执行SUB

Branching

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MOV R2 #17
B TARGET
ORR R1, R4, #14

TARGET
    SUB R1, R1, #78 ; TARGET就是Label

用汇编写C

1. MAX函数

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int main(){
    int max = 0, a = 2, b = 3;
    if (a < b)
        max = b;
    else
        max = a;
    return max;
}

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MAIN
    MOV R1 #2
    MOV R2 #3
    CMP R1 R2
    BLT LOWER

    MOV R0 R1
    B END
LOWER
    MOV R0 R2
    B END
END
    BX LR

2. 循环

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int main(){
    int a = 0;
    while (a < 4)
        a += 1;
    return a;
}

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MAIN
    MOV R0 #0
WHILE
    CMP R0 #4
    BEQ END
    ADD R0 #1
    B WHILE
END
    BX LR

3. 指数运算

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int pow = 1;
int x = 0;

while (pow !=128) {
    pow*=2;
    x+=1;
}

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R0 = pow, R1 = x
MOV R0 #1
MOV R1 #0

WHILE
    CMP R0 #128
    BEQ DONE
    LSL R0 #1
    ADD R1 #1

    B WHILE; 重复循环
DONE

附录

#代表立即数