modulefsm(inputclk,inputreset,inputx,outputregy);// Define states using Gray code
parameterS0=3'b000;
parameter S1 = 3'b001;parameterS2=3'b011;
parameter S3 = 3'b010;parameterS4=3'b110;
parameter S5 = 3'b111;// Declare state register and next state variable
reg[1:0]state,next_state;// Two procedural blocks for Moore-type FSM
always@(posedgeclkorposedgereset)beginif(reset)begin// Reset to initial state
state<=S0;y<=0;endelsebegin// Update current state based on next_state value at clock edge
state<=next_state;always@(*)begin// Next-state logic based on current-state and inputs (Mealy-type)
case(state)S0:if(x==1)begin// Transition to State-1 when x=1
next_state=S1;endelsebegin// Stay in the same State otherwise
next_state=S0;endS1:if(x==1)begin// Transition to State-2 when x=1
next_state=S2;endelsebegin// Stay in the same State otherwise
next_state=S1;endS2:if(x==0)begin// Transition to State-3 when x=0
next_state=S3;endelsebegin// Stay in the same State otherwise
next_state=S2;endS3:if(x==0)begin// Transition to State-0 when x=0
next_state=S0;endelsebegin// Stay in the same State otherwise
next_state=S3;endS4:if(x==0)next_state=S0;elsenext_state=S1;default:// Default transition to initial state (S0)
next_state=S0;endcaseendendmodule