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module fsm (
    input clk,
    input reset,
    input x,
    output reg y
);

// Define states using Gray code
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b011;
parameter S3 = 3'b010;
parameter S4 = 3'b110;
parameter S5 = 3'b111;

// Declare state register and next state variable
reg [1:0] state, next_state;

// Two procedural blocks for Moore-type FSM
always @(posedge clk or posedge reset) begin
    if (reset) begin
        // Reset to initial state
        state <= S0;
        y <= 0;
    end else begin
        // Update current state based on next_state value at clock edge
        state <= next_state;

always @(*) begin
    // Next-state logic based on current-state and inputs (Mealy-type)

     case(state)
         S0:
             if(x == 1) begin   // Transition to State-1 when x=1
                 next_state = S1;
             end else begin     // Stay in the same State otherwise
                 next_state = S0;
             end

         S1:
             if(x == 1) begin   // Transition to State-2 when x=1
                 next_state = S2;
             end else begin     // Stay in the same State otherwise
                 next_state = S1;
             end

         S2:
            if(x == 0) begin    // Transition to State-3 when x=0
                next_state = S3;
            end else begin      // Stay in the same State otherwise
                next_state = S2;
            end

         S3:
            if(x == 0) begin    // Transition to State-0 when x=0
                next_state = S0;
            end else begin      // Stay in the same State otherwise
                next_state = S3;
            end
         S4:
            if(x==0)
                next_state = S0;
            else
                next_state = S1;


         default:               // Default transition to initial state (S0)
             next_state = S0;
     endcase

end

endmodule

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module moore_101_sequence_detector(
    input clk,
    input reset,
    input data,
    output reg detected
);

parameter S0 = 2'b00; // 状态0
parameter S1 = 2'b01; // 状态1
parameter S2 = 2'b10; // 状态2
parameter S3 = 2'b11; // 状态3

reg [1:0] state; // 状态寄存器

always @(posedge clk, posedge reset) begin
    if (reset) begin
        state <= S0; // 复位状态
        detected <= 0; // 复位检测信号
    end 
    else begin
    case (state)
    S0: begin // 状态0
        if (data) begin
            state <= S1;
        end else begin
            state <= S0;
        end
    end
    S1: begin // 状态1
        if (data) begin
            state <= S1;
        end else begin
            state <= S2;
        end
    end
    S2: begin // 状态2
        if (data) begin
            state <= S3;
        end else begin
            state <= S0;
        end
    end
    S3: begin // 状态3
        if (data) begin
            state <= S1;
            detected <= 1; //检测到101
        end else begin
            state <= S2;
        end
        end
    endcase
    end
endmodule